A bus ring architecture includes a network topology in which data travels around a network ring. A plurality of agents are connected to the bus ring through switch units. Each agent can receive/transmit data around the ring through the switch units, where the switch units can also be used as repeaters for data flowing through the ring. The amount of data traffic that can flow through the bus ring at any time is limited by parameters such as the maximum bandwidth and frequency of the bus ring. Performance of the bus ring is said to be high when more data traffic can flow through the bus ring. However, high performance may mean that power consumption is increased, because higher frequency of operation leads to more power consumed by the bus ring. Thus, balancing performance and power consumption is a recognized design challenge for bus rings.
The agents connected to the bus ring can include processors (e.g., central processing units (CPUs), digital signal processors (DSPs), etc.), memory controllers, memory devices such as caches (e.g., L2, L3 caches), peripheral bridges, etc. The agents may have varying requirements and may influence the traffic on the bus rings differently. However, conventional bus ring designs take the overall bus ring traffic and frequency into account while trying to modulate performance of the bus ring and minimize power consumption. The conventional designs seek to reduce power consumption by slowing down the bus ring clock frequency and/or lowering the voltage of the bus ring circuits based on metrics such as average traffic in the bus ring. However, metrics related to the overall frequency or traffic of the bus ring are misleading because these metrics do not correlate well with the performance or needs of individual agents. Some agents may be stalled or starved while other agents may over-utilize the bus ring's resources. Lowering the frequency of the bus ring based on average traffic may further degrade the performance of the stalled agents. Conventional designs do not monitor the interfaces of individual agents (or more specifically, the interfaces of switch units) to determine if the performance requirements of the individual agents are satisfied. Moreover, in conventional designs, changes in the bus ring frequency are not based on concurrence of all agents, which may, for example, lead to depriving a starved agent from an opportunity to prevent further starvation that may be caused by a lowering of the bus ring frequency.
Accordingly, there is a need for improved performance monitoring to achieve reduced power consumption and increased efficiency of traffic flow in bus ring designs.